NASA is testing a chip that will enable spacecraft to make decisions independently.

About the HPSC Project

The Jet Propulsion Laboratory (JPL) of NASA in Southern California is testing a new processor as part of the High Performance Spaceflight Computing program. The project is implemented through a commercial partnership with Microchip Technology Inc. of Chandler, Arizona.

The goal of the program is to significantly increase the computing power of future spacecraft. Currently, NASA uses chips developed many years ago: they are reliable and resistant to space conditions, but their performance is no longer sufficient for autonomous missions, rapid processing of scientific data, and supporting crewed flights to the Moon and Mars.

Eugene Schwab, manager of the Game Changing Development program at NASA's Langley Research Center, noted that the new chip takes into account all accumulated experience in developing space processors. According to him, the multi-core architecture has made the system simultaneously reliable, flexible, and significantly more powerful than its predecessors.

What the Chip Is

HPSC is implemented as a system-on-a-chip (SoC) design, meaning all key computer components are placed on a single die. It includes central processing units, compute offload blocks, network modules, memory, and input/output interfaces. Such designs are also used in smartphones and tablets—but the NASA version is designed differently: it must operate for years at distances of millions and billions of kilometers from Earth, without the possibility of repair.

The processor is designed for performance up to 100 times higher than that of current onboard computers. According to initial test results, the actual performance figure turned out to be even higher—500 times.

How Testing Is Conducted

Testing at JPL began in February 2026 and will continue for several more months. Engineers are checking the chip's resistance to electromagnetic radiation, extreme temperature fluctuations, and mechanical shocks. High-energy particles from the Sun and interstellar space can cause errors that force the spacecraft into "safe mode"—shutting down non-essential systems until the issue is resolved.

A separate set of tests focuses on landing scenarios. Jim Butler, HPSC project manager at JPL, explained that the team is reproducing real landing conditions from past NASA missions—those very scenarios that under normal circumstances require bulky and power-hungry equipment to process the massive data streams from landing sensors.

As a symbolic start, the team sent the first email with the subject line "Hello Universe"—a reference to the classic "Hello World" test message from the early days of programming.

Intended Applications for the Processor

The technology is oriented toward three areas:

Autonomous spacecraft. Communication between Earth and Mars takes anywhere from several minutes to 24 minutes each way. Under such conditions, a spacecraft cannot wait for commands from Earth—it must make decisions independently. HPSC enables the execution of artificial intelligence algorithms directly onboard, without delay.

Scientific data. Modern missions collect vast amounts of information. The new processor will allow this data to be analyzed, compressed, and transmitted to Earth much faster, accelerating scientific discoveries.

Crewed missions. The chip is planned for use in living modules on the Moon and Mars, where the reliability of onboard systems is critically important.

After NASA certification, HPSC is intended to be integrated into orbital spacecraft, rovers, habitable modules, and deep-space missions. Microchip Technology is also considering adapting the technology for the aviation and automotive industries—early batches have already been delivered to partners in the defense and commercial aerospace sectors.